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cyf2018v, cyf2036v cyf2072v 18/36/72-mbit programmable multi-queue fifos cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-68336 rev. ** revised april 12, 2011 18/36/72-mbit programmable multi-queue fifos features memory organization ? industry?s largest first in first out (fifo) memory densities: 18-mbit, 36-mbit and 72-mbit ? selectable memory organization: 9, 12, 16, 18, 20, 24, 32, 36 up to 100-mhz clock operation unidirectional operation independent read and write ports ? supports simultaneous read and write operations ? reads and writes operate on independent clocks upto a maximum ratio of two enabling data buffering across clock domains ? supports multiple i/o voltage standard: low voltage complementary metal oxide semiconductor (lvcmos) 3.3 v and 1.8 v voltage standards. input and output enable control for write mask and read skip operations user configured multi-queue operating mode upto 8-queues mark and retransmit: resets read pointer to user marked position empty and full flags flow-through mailbox register to send data from input to output port, bypassing th e fifo sequence configure programmable flags and registers through serial or parallel modes separate serial clock (sclk) input for serial programming master reset to clear entire fifo joint test action group (jtag) port provided for boundary scan function industrial temperature range: ?40 c to +85 c functional description the cypress programmable fifo family offers the industry?s highest-density programmable fifo memory device. it has independent read and write ports, which can be clocked up to 100 mhz. user can configure in put and output bus sizes. the maximum bus size of 36 bits enables a maximum data throughput of 3.6 gbps. the read and write ports can support multiple i/o voltage standards. the user-programmable registers enable user to configure the device operation as desired. the device also offe rs a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs. this makes it an ideal memory choice for a wide range of applications including multiprocessor interfaces, video and image processing, networking and telecommunications, high-speed data acquisition, or any system th at needs buffering at very high speeds across different domains. as implied by the name, the functi onality of the fifo is such that the data is read out of the read port in the same sequence in which it was written into the writ e port. the data is sequentially written into the fifo from the write port. if the writes and inputs are enabled, the data on the write port gets written into the device at the rising edge of the write clock. enabling the reads and outputs fetches data on the read port at every rising edge of the read clock. both reads and writes can occur simultaneously at different speeds provided the ratio of read to write clock is in the range of 0.5 to 2. appropriate flags are set whenever the fifo is empty or full. the device also supports multi- queue operation upto 8 queues, mark and retransmit of data, and a flow-through mailbox register. all product features and specs are common to all densities (cyf2072v, cyf2036v, and cyf2018v) unless otherwise specified. all descriptions ar e given assuming the device is cyf2072v operated in 36 mode. they hold good for other densities (cyf2036v, and cyf2018v) and all port sizes 9, 12, 16, 18, 20, 24 a nd 32 unless otherwise specified. the only difference will be in the input and output bus width. table 1 on page 8 shows the part of bus with valid data from d[35:0] and q[35:0] in 9, 12 , 16, 18, 20, 24, 32 and 36 modes. [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 2 of 30 logic block diagram [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 3 of 30 contents pin diagram for cyf2xxxv ........ .............. .............. ......... 4 pin definitions .................................................................. 5 architecture ...................................................................... 7 reset logic ................................................................. 7 flag operation ............................................................. 7 full flag ....................................................................... 7 empty flag .................................................................. 7 retransmit from mark operation ................................. 7 flow-through mailbox register .................................... 7 selecting word sizes .......... ........................................ 7 data valid signal (dval) .............................................. 8 queue valid signal (qval[2:0]) ................................... 8 power up ........................................................................... 8 write mask and read skip oper ation ........... .............. 9 multi-queue operation ................................................ 9 width expansion configuration ............ .............. ....... 11 memory organization for different port sizes ........... 11 read/write clock requirements ............................... 12 jtag operation ............................................................... 13 maximum ratings ........................................................... 14 operating range ............................................................. 14 recommended dc operating conditions .................... 14 electrical characteristics ............................................... 14 i/o characteristics .......................................................... 15 latency table .................................................................. 15 switching characteristics .............................................. 16 switching waveforms .................................................... 17 ordering information ...................................................... 26 ordering code definitions ..... .................................... 26 package diagram ............................................................ 27 acronyms ........................................................................ 28 document conventions ................................................. 28 units of measure ....................................................... 28 document history page ................................................. 29 sales, solutions, and legal information ...................... 30 worldwide sales and design s upport ......... .............. 30 products .................................................................... 30 psoc solutions ......................................................... 30 [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 4 of 30 g pin diagram for cyf2xxxv figure 1. 209-ball fbga (top view) 1 2 3 4 5 6 7 8 9 10 11 aff d0 d1 wqsel0 portsz0 portsz1 dnu rqsel0 rt q0 q1 bef d2 d3 wqsel1 dnu portsz2 dnu rqsel1 ren q2 q3 cd4 d5 wen wqsel2 vcc1 dnu vcc1 rqsel2 rclk q4 q5 d d6 d7 vss vcc1 dnu ld dnu vcc1 vss q6 q7 e d8 d9 vcc2 vcc2 vccio vccio vccio vcc2 vcc2 q8 q9 f d10 d11 vss vss vss dnu vss vss vss q10 q11 g d12 d13 vcc2 vcc2 vccio vcc1 vccio vcc2 vcc2 q12 q13 h d14 d15 vss vss vss vcc1 vss vss vss q14 q15 j d16 d17 vcc2 vcc2 vccio vcc1 vccio vcc2 vcc2 q16 q17 k dnu dnu wclk dnu vss ie vss dnu vccio vccio vccio l d18 d19 vcc2 vcc2 vccio vcc1 vccio vcc2 vcc2 q18 q19 m d20 d21 vss vss vss vcc1 vss vss vss q20 q21 n d22 d23 vcc2 vcc2 vccio vcc1 vccio vcc2 vcc2 q22 q23 p d24 d25 vss vss vss spi_sen vss vss vss q24 q25 r d26 d27 vcc2 vcc2 vccio vccio vccio vcc2 vcc2 q26 q27 t d28 d29 vss vcc1 vcc1 spi_si vcc1 vcc1 vss q28 q29 udval dnu d30 d31 dnu dnu spi_sclk vref oe q30 q31 v qval1 qval0 d32 d33 dnu mrs mb dnu mark q32 q33 w tdo qval2 d34 d35 tdi trst tms tck vref q34 q35 [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 5 of 30 pin definitions pin name i/o pin description d[35:0] input data inputs: data inputs for a 36-bit bus. q[35:0] output data outputs: data outputs for a 36-bit bus. wen input write enable: wen enables wclk to write data into the fifo memory and configuration registers. ren input read enable: ren enables rclk to read data from the fi fo memory and configuration registers. ie input input enable: ie is the data input enable signal that controls the enabling and disabling of the 36-bit data input pins. if it is enabled, data on the d[35:0] pins is written into the fifo. the internal write address pointer is always incremented at rising edge of wclk if wen is enabled, regardless of the ie level. this is used for ?write masking? or incrementing t he write pointer without writing into a location. oe input output enable: when oe is low, fifo data outputs are enabled; when oe is high, the fifo?s outputs are in high z (high impedance) state. wclk input write clock: when enabled by wen , the rising edge of wclk writes data into the fifo if ld is high and into the configuration registers if ld is low. rclk input read clock: when enabled by ren , the rising edge of rclk reads data from the fifo memory if ld is high and from the configuration registers if ld is low. ef output empty flag: when ef is low, the queue is empty. ef is synchronized to rclk. ff output full flag: when ff is low, the queue is full. ff is synchronized to wclk. ld input load: when ld is low, d[7:0] (q[7:0]) are writt en (read) into (from) the configuration registers. when ld is high, d[35:0] (q[35:0]) are written (read) into (from) the fifo. rt input retransmit: a high pulse on rt resets the internal read pointer to a physical location of the fifo which is marked by the user (using mark pin). with every valid read cycle af ter retransmit, previously accessed data is read and the read pointer is increment ed until it is equal to the write pointer. mrs input master reset: mrs initializes the read and write pointers to ze ro and sets the output register to all zeroes. during master reset, the configuration registers ar e all set to default values and the flags are reset. spi_sclk input serial clock: a rising edge on spi_sclk clocks t he serial data present on the spi_si input into the offset registers if spi_sen is enabled. spi_si input serial input: serial input when spi_sen is enabled. spi_sen input serial enable: enables serial loading of prog rammable flag offsets and configuration registers. mark input mark for retransmit: when this pin is asserted th e current location of the read pointer is marked. any subsequent retransmit operation resets the read pointer to this position. mb input mailbox: when asserted the reads and wr ites happen to flow-through mailbox register. wqsel[2:0] input write queue select: sele ct maximum eight queues using pins. rqsel[2:0] input read queue select: select maximum eight queues using pins. tck input test clock (tck) pin for jtag. trst input reset pin for jtag. tms input test mode sele ct (tms) pin for jtag. tdi input test data in (tdi) pin for jtag. tdo output test data out (tdo) for jtag. dval output data valid: active low data valid signal to indicate valid data on q[35:0]. [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 6 of 30 qval[2:0] queue valid : bus along with dval indicating the queue for which data is being read out on q[35:0] dval = 0 and qval = 000 valid data read out from queue-0 on q[35:0] dval = 0 and qval = 001 valid data read out from queue-1 on q[35:0] dval = 0 and qval = 010 valid data read out from queue-2 on q[35:0] dval = 0 and qval = 011 valid data read out from queue-3 on q[35:0] dval = 0 and qval = 100 valid data read out from queue-4 on q[35:0] dval = 0 and qval = 101 valid data read out from queue-5 on q[35:0] dval = 0 and qval = 110 valid data read out from queue-6 on q[35:0] dval = 0 and qval = 111 valid data read out from queue-7 on q[35:0] portsz [2:0] input port word size se lect: port word width select pins (common for read and write ports). vcc1 power supply core voltage supply 1: 1.8 v supply voltage vcc2 power supply core voltage supply 2: 1.5 v supply voltage vccio power supply supply for i/os vref input reference reference voltage: reference voltage (regardless of i/o standard used) vss ground ground dnu ? do not use: these pins need to be left floating. pin definitions (continued) pin name i/o pin description [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 7 of 30 architecture the cyf2072v, cyf2036v, and cyf2018v are of memory arrays of 72-mbit, 36-mbit, and 18-mbit respectively. the memory organization is user configurable and word sizes can be selected as 9, 12, 16, 18, 20, 24, 32, or 36. the logic blocks to implement fifo functionality and the associated features are built aroun d these memory arrays. the input and output data buses have a maximum width of 36 bits configurable through portsz[2:0]. the input data bus goes to an input register and the data flow from the input register to the memory is controlled by the write logic block. the inputs to the write logic block are wclk, wen , ie , and wqsel[2:0]. when the writes are enabled through wen and if the inputs are enabled by ie , then the data on the input bus is written into the memory array at the rising edge of wclk. this also increments the write pointer. enabling writes but disabling the data input pins through ie only increments the write pointer without doing any writes or altering the contents of the location. wqsel[2:0] selects the queue in which the write should occur. similarly, the output register is connected to the data output bus. transfer of contents from the memory to the output register is controlled by the read control logic. the inputs to the read control logic include rclk, ren , oe , rqsel[2:0], mark and rt. when reads are enabled by ren and outputs are enabled through oe , the data from the memory pointed by the read pointer is transferred to the out put data bus at the rising edge of rclk along with active low dval . qval[2:0] indicates the queue number for which the read data belongs to. if the outputs are disabled but the reads enabled, the outputs are in high impedance state, but internally the read pointer is incremented. rqsel[2:0] selects the queue from which the read occurs. the mark signal is used to ?mark? the location from which data is retransmitted when requested. during write operation, the number of writes performed is always a even number (i.e., minimum write burst length is two and number of writes always a multip le of two). whereas during read operation, the number of reads performed can be even or odd (i.e., minimum read burst length is one). by default, the fifo is accessed as a single queue device. it is possible to divide the whole memory space into 2, 4 or 8 equal sized arrays. for more more explanation please refer to multi-queue operation on page 9 . reset logic the master reset (mrs ) initializes the read and write pointers to zero, sets the output register s to zero and sets the status of the flags to ff deasserted and ef asserted. mrs also resets the configuration register and t he mark address to their default values. mrs configures the device into single queue mode. a mrs is required after power up before accessing the fifo. after mrs , a minimum latency of 1024 clocks is necessary before the first access. the word size is configured through pins; values of the three portsz pins are latched on rising edge of mrs .after mrs , the device is configured in single queue mode by default. flag operation this device provides two flag pins to indicate the condition of the fifo contents. full flag the full flag (ff ) goes low when the device is full. all write operations are inhibited whenever ff is low regardless of the state of wen . ff is synchronized to wclk, that is, it is exclusively updated by each rising edge of wclk. the worst case assertion latency for full flag is four. as the user cannot know that the fifo is full for f our clock cycles, it is possible that user continues writing data during th is time. in this case, the four data word written will be stored to prevent data loss and these words have to be read back in order for full flag to get de-asserted. in 2q/4q/8q mode, ff indicates the status of the queue selected by wqsel[2:0]. the minimum number of reads required to de-assert full-flag is two and the maximum number of reads required to de-assert full flag is six. the assertion and de-assertion of full flag with associated latencies is explained in latency table on page 15 . empty flag the empty flag (ef ) goes low when the device is empty. all read operations are ignored whenever ef is low, regardless of the state of ren . ef is synchronized to rclk, i.e., it is exclusively updated by each risi ng edge of rclk. in 2q/4q/8q mode, ef indicates the status of the queue selected by rqsel[2:0]. the assertion and de-assertion of empty flag with associated latencies is explained in latency table on page 15 . retransmit from mark operation the retransmit feature is useful for transferring packets of data repeatedly. it enables the receip t of data to be acknowledged by the receiver and retransmitted if necessary. the retransmit feature is used when the number of writes equal to or less than the depth of the fifo has occurred ? and at least one word has been read since the last reset cycle. a high pulse on rt resets the internal read pointer to a physical location of the fifo that is marked by the user (using the mark pin). in multi-queue mode the mark and rt signals are validated with rqsel[2:0], i.e., mark or retransmit function will be performed for the queue that is selected by rqsel[2:0] . with every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. data written to fifo after activation of rt are also transmitted. the full depth of the fifo can be repeatedly retransmitted. to mark a location, the mark pin is asserted when reading that particular location. flow-through mailbox register this feature transfers data from input to output directly by bypassing the fifo sequence. when mb signal is asserted the data present in d[35:0] will be available at q[35:0] after two wclk cycles. normal read and writ e operations are not allowed during flow-through mailbox operation. before starting flow-through mailbox operation fifo read should be completed to make data valid (dval ) high in order to avoid data loss from fifo. the width of flow-thr ough mailbox register always corresponds to port size. selecting word sizes the word sizes are configured based on the logic levels on the portsz pins during the master reset (mrs ) cycle only (latched [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 8 of 30 on low to high edge). the port size cannot be changed during normal mode of operation and these pins are ignored. if word size is less than 36, the unused output pins are tri-stated by the device.and unused input pins will be ignored by the internal logic. the pins with valid data input d[ n:0] and output q[n:0] is given in ta b l e 1 . data valid signal (dval ) data valid (dval ) is an active low signal and is provided for easy capture of output data to the user. when a read operation is performed, the dval signal goes low along with output data. this helps user to capture the data without keeping track of ren to data output latency. this signal also helps when write and read operations are performed continuo usly at different frequencies by indicating when valid data is available at the output port q[35:0]. queue valid signal (qval[2:0]) queue valid (qval[2:0]) is a thr ee bit output that indicates the queue from which valid data is being read. with respect to data this bus has to be validated along with the dval signal. when dval signal is high, the values on this bus can be ignored. power up the device becomes functional after v cc1 , v cc2 , v ccio , and vref attain minimum stable voltage required as given in recommended dc operating conditions on page 14 . the device can be accessed in t pu time after these supplies attain the minimum required level (see switching characteristics on page 16 ). there is no power sequencing required for the device. table 1. word size selection portsz[2:0] word size active input data pins d[x:0] active output data pins q[x:0] 000 9 d[8:0] q[8:0] 001 12 d[11:0] q[11:0] 010 16 d[15:0] q[15:0] 011 18 d[17:0] q[17:0] 100 20 d[19:0] q[19:0] 101 24 d[23:0] q[23:0] 110 32 d[31:0] q[31:0] 111 36 d[35:0] q[35:0] table 2. multi-queue configuration operating mode (given by configuration register 0x3 [2:0]) rqsel[2:0]/wqsel[2:0] queue number selected 1q mode (register 0x3[2:0]= 3?b000) 000 0 001-111 invalid 2q mode (register 0x3[2:0]= 3?b001) 000 0 001 1 010-111 invalid 4q mode (register 0x3[2:0]= 3?b01x) 000 0 001 1 010 2 011 3 100-111 invalid 8q mode (register 0x3[2:0]= 3?b1xx) 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 9 of 30 write mask and read skip operation as mentioned in architecture on page 7 , enabling writes but disabling the inputs (ie high) increments the write pointer without doing any write operations or altering the contents of the location. this feature is called write mask and allows user to move the write pointer without actually writ ing to the locations. this ?write masking? ability is useful in some video applications such as picture in picture (pip). similarly, during a read operatio n, if the outputs are disabled by having the oe high, the read data does not appear on the output bus; however, the read pointer is incremented. multi-queue operation in general, the entire memory space is accessed as a single fist in first out (fifo) order for the write and read operation. in this case, the entire memory space is called a single queue. for example, for 72m device, the entire memory space is available as a single fifo memory. in multi queue mode , the entire memory space is divided into equal sized memory array and each individual memory arra y can be accessed as an independent fifo based on additi onal control signals. these independent memory arrays are called as queues. for example, when 72m device, is configured into eight queue mode, the entire memory space of 72m is divided into eight 9m memory array called as queue-0 to queue-7. these queues can be accessed independently as a fi fo by selecting the queue select signals wqsel[2:0] and rqsel[2:0]. in this way, upto eight queues can be created for a given device where data can be stored independently and read out independently. it is possible to configure the whole memory space of cyf2072v into 8 or 4 or 2 equal sized array, and each array can be independently accessed as an in dependent fifo. this is like having eight or four or two independent queues inside the fifo instead of entire memory space acting as single queue fifo. the number of queues is confi gured based on the value of d2, d1 & d0 bit of configuration register 0x3 (refer to ta b l e 3 ). table 2 on page 8 shows the value to be set in d2, d1 & d0 of configuration register 0x3 to configure the device in 1/2/4/8 queue modes. . table 3. configuration registers addr configuration register default bit [7] bit [6] bit [5] bit [4] bit [3] bit [2] bit [1] bit [0] 0x1 reserved 0x00 x x x x x x x x 0x2 reserved 0x00 x x x x x x x x 0x3 number of queues 0x00 enable queue registers x x x x d2 d1 d0 0x4 reserved 0x7f x x x x x x x x 0x5 reserved 0x00 x x x x x x x x 0x6 reserved 0x00 x x x x x x x x 0x7 reserved 0x7f x x x x x x x x 0x8 reserved 0x00 x x x x x x x x 0x9 reserved 0x00 x x x x x x x x 0xa fast clk bit register 1xxxxxxxb fast clk bit xx x x x x x table 4. writing and reading configuration registers in parallel mode spi_sen ld wen ren wclk rclk spi_sclk operation 1001 ? first rising edge because both ld and ren are low x x parallel write to first register 1001 ? second rising edge x x parallel write to second register 1001 ? third rising edge x x parallel write to third register 1001 ? fourth rising edge x x parallel write to fourth register 1001 ?? xx ?? 1001 ?? xx ?? 1001 ?? xx ?? 1001 ? tenth rising edge x x parallel write to tenth register [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 10 of 30 1001 ? eleventh rising edge x x parallel write to first register (roll back) 1010 x ? first rising edge since both ld and ren are low x parallel read from first register 1010 x ? second rising edge x parallel read from second register 1010 x ? third rising edge x parallel read from third register 1010 x ? fourth rising edge x parallel read from fourth register 1010 x ?? x ?? 1010 x ?? x ?? 1010 x ?? x ?? 1010 x ? tenth rising edge x parallel read from tenth register 1010 x ? eleventh rising edge x parallel read from first register (roll back) 1 x 1 1 x x x no operation x10x ? rising edge x x write to fifo memory x1x0 x ? rising edge x read from fifo memory 0 0 x 1 x x x illegal operation table 5. writing into configuration registers in serial mode spi_sen ld wen ren wclk rclk sclk operation 01xx x x ? rising edge each rising of the sclk clocks in one bit from the si (serial in). any of the 10 registers can be addressed and written to, following the spi protocol. x10x ? rising edge x x parallel write to fifo memory. x1x0 x ? rising edge x parallel read from fifo memory. 1 0 1 1 x x x this corresponds to parallel mode (refer to ta b l e 4 ). table 4. writing and reading configuration registers in parallel mode (continued) spi_sen ld wen ren wclk rclk spi_sclk operation [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 11 of 30 width expansion configuration the width of cyf2072v can be expanded to provide word widths greater than 36 bits. during width expansion mode, all control line inputs are common and all flags are available. empty (full) flags are created by anding the em pty (full) flags of every fifo. this technique avoids reading data from or writing data to the fifo that is ?staggered? by one clock cycle due to the variations in skew between rclk and wclk. figure 3 on page 11 demonstrates an example of a 72 bit-word width by using two 36-bit word cyf2072vs. memory organization for different port sizes the 72-mbit memory has different organization for different port sizes. table 6 shows the depth of the fifo for all port sizes. note that for all port sizes, four to eight locations are not available for writing the data and are used to safeguard against false synchronization of empty and full flags. the memory size mentioned is when the device is configured in single-queue mode. figure 2. serial write to configuration register figure 3. using two cyf2072vs for width expansion ff ff ef ef write clock (wclk) write enable (wen ) ff cyf2072v cyf2072v 36 72 datain (d) 36 read clock (rclk) read enable (ren ) output enable(oe ) 36 dataout (q) 36 72 ef table 6. word size selection portsz[2:0] word size fifo depth memory size 000 9 8 meg 72 mbit 001 12 4 meg 48 mbit 010 16 4 meg 64 mbit 011 18 4 meg 72 mbit 100 20 2 meg 40 mbit 101 24 2 meg 48 mbit 110 32 2 meg 64 mbit 111 36 2 meg 72 mbit [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 12 of 30 read/write clock requirements the read and write clocks must satisfy the following requirements: both read (rclk) and write (wclk) clocks should be free-running. the clock frequency for both clocks should be between the minimum and maximum range given in switching characteristics on page 16 . the ratio of rclk to wclk should be in the range of 0.5 to 2. for proper fifo operation, the device must determine which of the input clocks ? rclk or wclk ? is faster. this is evaluated by using counters after the mrs cycle. the device uses two 10-bit counters inside (one running on rclk and other on wclk), which count 1,024 cycles of read and write clock after mrs . the clock of the counter which reaches its terminal count first is used as master clock inside the fifo. when there is change in the relative frequency of rclk and wclk during normal operation of fifo, user can specify it by using ?fast clk bit? in the configuration register (0xa). ?1? - indicates f req (wclk) > f req (rclk) ?0? - indicates f req (wclk) < f req (rclk) the result of counter evaluated frequency is available in this register bit. user can override the counter evaluated frequency for faster clock by changing this bit. whenever there is a change in this bit value, user must wait t pll time before issuing the next read or write to fifo. [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 13 of 30 jtag operation cyf2xxxv has two devices connected inter nally in a jtag chain as shown in figure 4 . figure 4. jtag operation ta b l e 7 shows the ir register length and device id. for boundary scan, device-1 should be in bypass mode. ta b l e 8 and ta b l e 9 shows the jtag instruction set for devices 1 and 2 respectively. table 7. jtag idcodes ir register length device id (hex) bypass register length device-1 3 ?ignore? 1 device-2 8 1e3261cf 1 table 8. jtag instructions device-1 opcode (binary) bypass 111 table 9. jtag instructions device-2 opcode (hex) extest 00 highz 07 sample/preload 01 bypass ff idcode 0f [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 14 of 30 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature (without bias) ......... ?65 ? c to +150 ? c ambient temperature with power applied .......................................... ?55 ? c to +125 ? c core supply voltage 1 (vcc1) to ground potential......................... .....................?0.3 v to 2.5 v core supply voltage 2 (vcc2) to ground potential............................................?0.3 v to 1.65 v latch-up current ....... ............. ............. ............ .....> 100 ma i/o port supply voltage (vccio). .............. ......?0.3 v to 3.7 v voltage applied to i/o pins............................?0.3 v to 3.75 v output current into outputs (low) .............................. 20 ma static discharge voltage........................................... > 2001 v (per mil?std?883, method 3015) operating range range ambient temperature industrial ?40 ? c to +85 ? c recommended dc operating conditions parameter description min typ max unit vcc1 core supply voltage 1 1.70 1.80 1.90 v vcc2 core supply voltage 2 1.425 1.5 1.575 v vref reference voltage (irrespective of i/o standard used) 0.7 0.75 0.8 v vccio i/o supply voltage, read and write banks. lvcmos33 3.00 3.30 3.60 v lvcmos18 1.70 1.8 1.90 v electrical characteristics parameter description conditions min typ max unit i cc active current v cc1 = v cc1max ?? 300 ma v cc2 = v cc2max , all i/o switching, 100 mhz ?? 500 ma v ccio = v cciomax (all outputs disabled) ?? 100 ma i i input pin leakage current v in = v cciomax to 0 v ?15 ? 15 a i oz i/o pin leakage current v o = v cciomax to 0 v ?15 ? 15 a c p capacitance for tms and tck ???16pf c pio capacitance for pins apart from tms and tck ???8pf [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 15 of 30 figure 5. ac test load conditions i/o characteristics i/o standard nominal i/o supply voltage input voltage (v) output voltage (v) output current (ma) v il (max) v ih (min) v ol (max) v oh (min) i ol (max) i oh (max) lvcmos33 3.3 v 0.80 2.20 0.45 2.40 24 24 lvcmos18 1.8 v 30% v ccio 65% v ccio 0.45 v ccio ? 0.45 16 16 latency table latency parameter number of cycles detail l ff _assert min = 0 max = 4 last data write to ff going low l ef _assert 0 last data read to ef going low l rqsel_change 1 minimum rclk cycles before rqsel[2:0] can change l wqsel_change 2 minimum wclk cycles before wqsel[2:0] can change l mailbox 2 latency from write port to read port when mb = 1 (w.r.t wclk) l ren _to_data 4 latency when ren is asserted low to first data output from fifo l ren _to_config 4 latency when ren is asserted along with ld to first data read from configuration registers l ff _deassert 7 read to ff going high l rt_to_ren 9 rt 5th cycle to ren going low for read l rt_to_data min = 22 max = 24 rt 5th cycle to valid data on q[35:0] l in min = 30 max = 31 initial latency for data read after fifo goes empty during simultaneous read/write l ef _deassert min = 28 max = 29 write to ef going high (a) v ccio = 1.8 volt (b) v ccio = 3.3 volt (c) all input pulses [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 16 of 30 switching characteristics over the operating range parameter description -100 unit min max t pu power-up time after all supplies reach minimum value ? 2 ms t s clock cycle frequency 3.3 v lvcmos 24 100 mhz t s clock cycle frequency 1.8 v lvcmos 24 100 mhz ta data access time ? 10 ns t clk clock cycle time 10 41.67 ns t clkh clock high time 4.5 ? ns t clkl clock low time 4.5 ? ns t ds data setup time 3 ? ns t dh data hold time 3 ? ns t qs rqsel and wqsel setup time 3 ? ns t qh rqsel and wqsel hold time 3 ? ns t ens enable setup time 3 ? ns t enh enable hold time 3 ? ns t ens_si setup time for si and sen in spi mode 5 ? ns t enh_si hold time for si and sen in spi mode 5 ? ns t rate_spi frequency of sclk ? 25 mhz t rs reset pulse width 100 ? ns t pzs port size select to mrs seup time 25 ? ns t pzh mrs to port size select hold time 25 ? ns t rsf reset to flag output time ? 50 ns t prt retransmit pulse width 5 ? rclk cycles t olz output enable to output in low z 4 15 ns t oe output enable to output valid ? 15 ns t ohz output enable to output in high z ? 15 ns t wff write clock to ff ?9.5ns t ref read clock to ef ?9.5ns t pll time required to synchronize pll ? 1024 cycles t rate_jtag jtag tck cycle time 100 ? ns t s_jtag setup time for jtag tms,tdi 8 ? ns t h_jtag hold time for jtag tms,tdi 8 ? ns t co_jtag jtag tck low to tdo valid ? 20 ns [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 17 of 30 switching waveforms figure 6. write cycle timing figure 7. read cycle timing figure 8. reset timing t clkh t clkl no operation t ds t ens wen , ie t clk t dh t enh wclk d[35:0] no operation t clk t ohz rclk q[35:0] ren oe t ens t olz t a t enh valid data l ren _to_data dval t rs q[35:0] mrs t rsf t rsf t rsf oe =1 oe =0 ef ff [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 18 of 30 figure 9. mrs to portsz[2:0] figure 10. flow-through mailbox operation switching waveforms (continued) wclk/rclk portsz[2:0] mrs t pzs t pzh wclk d[35:0] ren / wen mb do d1 d3 q4 q1 q2 qo q3 q[35:0] d2 d4 dval 1 23 l mailbox [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 19 of 30 figure 11. configuration register write figure 12. configuration register read figure 13. wqsel to ff ld d[35:0] config-reg 0 config-reg 1 config-reg 2 config-reg 3 config-reg 4 config-reg 5 wclk wen / ie t ens t ds t dh wclk /rclk ren ld q[35:0] reg - 1 l ren _to_config 5 4 3 2 1 0 ff for que-5 ff for que-4 ff for que-3 ff for que-2 ff for que-1 ff for que-0 t qs t wff wclk wqsel[2:0] ff [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 20 of 30 figure 14. rqsel to ef figure 15. write to empty flag de-assertion ef for que-6 ef for que-5 ef for que-4 ef for que-3 ef for que-2 5 27 6 5 4 3 4 3 2 1 1 0 rclk rqsel[2:0] ef ef for que-1 ef for que-0 t qs t ref l ren_to_data d1 d0 0 wclk rclk ren ef d[35:0] wen 12345 27 26 25 ef for que-0 wqsel[2:0]/ rqsel[2:0] l ef_deassert [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 21 of 30 figure 16. read to empty flag assertion figure 17. full flag assertion 0 wqsel[2:0]/ rqsel[2:0] rclk 12345 q[35:0] q0 dval ef ef for que-0 ren t ref l ren_to_data d 0 0 wqsel[2:0]/ rqsel[2:0] wclk wen d[35:0] d 1 d 2 d x d last-1 d last not written not written t wff ff [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 22 of 30 figure 18. full flag de-assertion figure 19. switching between queues - write 0 wqsel[2:0]/ rqsel[2:0] 0 wqsel[2:0]/ rqsel[2:0] wclk wen d[35:0] ff d last-4 d last-3 d last-2 d last-1 d last rclk ren l ff_deassert d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 d1 d0 wqsel[2:0] data for que-5 data for que-4 data for que-3 data for que-2 data for que-1 data for que-0 wclk 5 4 3 2 1 0 d[35:0] wen [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 23 of 30 figure 20. switching between queues - read q0 q0 q0 q0 q0 q0 q0 q0 qval[2:0] dval t qs 26 5 4 3 1 0 q[35:0] que-5 data que-3 data que-1 data 7 que-6 data que-4 data que-2 data que-0 data 5 26 5 4 3 4 3 2 1 1 0 rclk rqsel[2:0] ren l ren_to_data [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 24 of 30 figure 21. simultaneous write & read que - 0 0 0 wqsel[2:0]/ rqsel[2:0] wclk wen d[35:0] d 0 d 1 d 2 d 3 rclk ren q 0 q 1 q 2 q 3 d n d n+1 d n+2 d n+3 q[35:0] dval l in (initial latency) 0 qval[2:0] [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 25 of 30 figure 22. mark figure 23. retransmit 0 rqsel[2:0] 0 dval rclk mark ren q[35:0] q (n-1) q (n) q (n+1) data marked in que-0 q (n+3) q (n+2) q (n+5) q (n+4) q (n+6) q (n-2) 0 qval[2:0] rqsel[2:0] 0 retransmit from data marked in que-0 q (n+1) q (n) dval rt_fl rclk ren q[35:0] t prt 0 qval[2:0] l rt_to_ren l rt_to_data [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 26 of 30 ordering information speed (mhz) ordering code package diagram package type operating range 100 CYF2018V33L-100BGXI 51-85167 209-ball fine-pitch ball grid array (fbga) (14 22 1.76 mm) industrial cyf2036v33l-100bgxi cyf2072v33l-100bgxi cyf2018v18l-100bgxi cyf2036v18l-100bgxi cyf2072v18l-100bgxi ordering code definitions i/o voltage: 18 = 1.8v density: 018 = 18m cypress cy f x xxx vxx x - xxx bgxi fifo i/o standard: l = lvcmos 036 = 36m 072 = 72m 33 = 3.3 v speed: 100 mhz 2 - multi-queue (8 queues) [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 27 of 30 package diagram figure 24. 209-ball fbga (14 22 1.76 mm), 51-85167 51-85167 *a [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 28 of 30 acronyms document conventions units of measure acronym description ff full flag fifo first in first out ie input enable i/o input/output fpbga fine-pitch ball grid array jtag joint test action group lvcmos low voltage complementary metal oxide semiconductor mb mailbox mrs master reset oe output enable rclk read clock ren read enable rclk read clock rqsel read queue select sclk serial clock tdi test data in tdo test data out tck test clock tms test mode select wclk write clock wen write enable wqsel write queue select que-0 queue number 0 symbol unit of measure c degree celsius ? a micro amperes ma milli amperes ms milli seconds mhz mega hertz ns nano seconds ? ohms pf pico farad v volts w watts [+] feedback [+] feedback
cyf2018v, cyf2036v cyf2072v document number: 001-68336 rev. ** page 29 of 30 document history page document title: cyf2018v/cyf2036v/cyf2072v, 18/36/72-mbit programmabl e multi-queue fifos document number: 001-68336 rev. ecn no. orig. of change submission date description of change ** 3209860 sivs 03/30/2011 new data sheet [+] feedback [+] feedback
document number: 001-68336 rev. ** revised april 12, 2011 page 30 of 30 all products and company names mentioned in this document may be the trademarks of their respective holders. cyf2018v, cyf2036v cyf2072v ? cypress semiconductor corporation, 2011. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rig hts. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with cypres s. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback [+] feedback

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